Data storage applications (for example, solid state drives, hard disk drives, and the like) may use low density parity check (LDPC) to correct errors that occur when storing and reading, or sending and receiving information. One design choice in planning LDPC coding systems is an amount of redundancy (ECC parity bits) used to meet the product specification. This redundancy is represented by the code rate of an LDPC code, which is equal to the user data length divided by the total number of bits stored. The general trend is that the lower the code rate is (more redundancy added), the better protection of the user data, and better performance in error detection and correction. If the code rate is chosen too high, the device may fail before the targeted program/erasure lifetime due to increasing error rates. On the other hand, if the code rate is chosen too low, extra storage space is wasted. Different LDPC encoder/decoder designs are implemented for different code rates, and for different chips/technologies or applications. Devices from different manufacturers may utilize different code rates, and, in that regard, code rates may span a wide range.
A flash memory chip has vastly different behavior at the beginning of life (“BOL”) and at end of life (“EOL”) scenarios. In particular, the data error rates from the flash memory chip increase dramatically as the flash memory chip ages. For example, the raw bit error rate (“BER”) produced during read operations may increase by a magnitude of 100 between 1K and 30K program/erase (“P/E”) cycles.